IEC 62418:2010 pdf free download

IEC 62418:2010 pdf free download Semiconductor devices – Metallization stress void test
This International Standard describes a method of metallization stress void test andassociated criteria. lt is applicable to aluminium (Al) or copper(Cu) metallization.
This standard is applicable for reliability investigation and qualification of semiconductorprocess.
2 Test equipment
A calibrated hot chuck or thermal chamber is required to subject the wafers or packaged teststructures to the specified temperature (15 °C) for the specified time. For resistancemeasurements dedicated equipment is needed.For void inspection deprocessing equipmentis required to remove the scratch protection layer. The inspections are performed with ascanning electron microscope (SEM).
3 Test structure
3.1 Test structure patterns
Test structures shall be used for all metal layers which have to be inspected and severaldifferent types of structure may be used. The following two types of test structures areapplicable for this test standard.
NOTE For metallization without refractory shunt layers reflective notching at steps can occur in test structureswith underlying topography, which will therefore tend to indicate a relatively worse stress-voiding behaviour.
3.2 Line pattern
Parallel lines which are patterned at the minimum linewidth allowed by design form anappropriate test structure.Unless otherwise specified a minimum length of 500 um and a totallength of 1 cm to 1 000 cm are recommended condition. Single long isolated lines arerecommended because stress voiding is often sensitive to line-to-line separation.
NOTE1 Narrow lines are susceptible for stress voiding because the stress in the metal is typically higher innarrower lines than in wider lines.
NOTE 2 The line length should be sufficient to insure that void nucleation sites will exist.3.3via chain pattern
3.3.1Pattern types
A via chain pattern is applicable as a test structure.For technology investigations a Kelvin-pattern for four-point measurements may also be used.
3.3.2 Pattern for aluminium(Al) process
Via chains need to consist of a pattern of vias connected by minimum linewidth. Therecommended number of vias is between 1 000 and 10o o0o. it is recommended to useisolated and long minimum linewidths.
3.3.3 Pattern for copper (Cu) process
For Cu metallization the following structures are applicable:
a) via chains with top and bottom metal segments with minimum allowed width;
b) via chains with either the top or the bottom metal segment at minimum allowed width, and
the other segment at the maximum width allowed for a single via;
c) vias chains with both top and bottom metal segments at the maximum width allowed for a
single via;
d) Kelvin via structures, with various widths for top and bottom metal.Chains with 1 0o0 – 100 ooo vias are recommended.
4Stress temperature
To evaluate the impact of stress voiding on chip reliability under use conditions,acceleratedtesting is needed to generate voiding.The acceleration factor can be strongly affected by thefactors listed in Annex B and Annex C.Therefore, it is recommended to determine empiricallythe temperature range for accelerated testing which will maximize voiding.Recommendedtemperature ranges are given in 5.2 and 5.3.